Difference between revisions of "SpeedStep"
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| − | On January 18th, 2000, Intel released its Mobile Pentium 3 600 MHz CPU with | + | On January 18th, 2000, Intel released its Mobile Pentium 3 600 MHz CPU with a proprietary [[Power Management|power management]] technology called SpeedStep. This technology basically provides additional power saving modes for Intel's CPUs, it does not provide any sort of performance improvement. |
| − | + | Please note that every revision of SpeedStep are similar and may be confusing, therefore this page will attempt to document the behavior of every known SpeedStep revision. | |
|} | |} | ||
==Released== | ==Released== | ||
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Under AC power (in a charging or non-charging state), SpeedStep will automatically step into 'Maximum Performance Mode'. If the AC adapter is disconnected from the system, SpeedStep will automatically step into 'Battery Optimized Mode'. This behavior can be modified to some extent via issuing an instruction to either step into 'Maximum Performance Mode' without AC power, or step into 'Battery Optimized Mode' with AC power. | Under AC power (in a charging or non-charging state), SpeedStep will automatically step into 'Maximum Performance Mode'. If the AC adapter is disconnected from the system, SpeedStep will automatically step into 'Battery Optimized Mode'. This behavior can be modified to some extent via issuing an instruction to either step into 'Maximum Performance Mode' without AC power, or step into 'Battery Optimized Mode' with AC power. | ||
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| + | The 'Coppermine' Mobile Pentium 3 used this revision of SpeedStep. No other Intel CPU has used this revision of SpeedStep. | ||
===Enhanced Intel SpeedStep Technology (Geyserville-2)=== | ===Enhanced Intel SpeedStep Technology (Geyserville-2)=== | ||
| − | This was a minor revision of the first SpeedStep that added a new feature called 'Demand-Based | + | This was a minor revision of the first SpeedStep that added a new feature called 'Demand-Based Switching'. The DBS function alters the CPU's current power mode state via monitoring the CPU's load, by making it operate in 'Maximum Performance Mode' under high to normal usage, and in 'Battery Optimized Mode' under low to no usage. |
There were no major changes made to SpeedStep's behavior, other than the fact that the transition between the two basic power modes were now controlled by the DBS feature. However, SpeedStep could still be issued an instruction to always stay in 'Maximum Performance Mode' or 'Battery Optimized Mode'. | There were no major changes made to SpeedStep's behavior, other than the fact that the transition between the two basic power modes were now controlled by the DBS feature. However, SpeedStep could still be issued an instruction to always stay in 'Maximum Performance Mode' or 'Battery Optimized Mode'. | ||
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This was a major revision of SpeedStep, which removed the overly simple 'two power modes with hard-wired predefined values' concept. It now has the ability to operate on a wide range of frequencies by switching the CPU's clock multiplier (by 1x steps, not 0.5x steps), which was not the case for the two previous revisions of SpeedStep. Additionally, it has the capability of controlling the CPU's core voltage with more precision (by 16 mV steps, or lesser depending on the CPU model), unlike the previous revisions which used only two core voltages. | This was a major revision of SpeedStep, which removed the overly simple 'two power modes with hard-wired predefined values' concept. It now has the ability to operate on a wide range of frequencies by switching the CPU's clock multiplier (by 1x steps, not 0.5x steps), which was not the case for the two previous revisions of SpeedStep. Additionally, it has the capability of controlling the CPU's core voltage with more precision (by 16 mV steps, or lesser depending on the CPU model), unlike the previous revisions which used only two core voltages. | ||
| − | As SpeedStep was re-worked to take advantage of the aforementioned features, the behavior was also re-worked as well. In addition to the capability of controlling core voltage and clock frequencies via DBS, it is also capable of shutting down parts of the CPU to reduce power consumption, such as the L2 cache. In certain cases, the DBS feature (only from this revision of SpeedStep) is also known to utilize clock-gating to further reduce power consumption. | + | As SpeedStep was re-worked to take advantage of the aforementioned features, the behavior was also re-worked as well. In addition to the capability of controlling core voltage and clock frequencies via DBS, it is also capable of shutting down parts of the CPU to reduce power consumption, such as the L2 cache. In certain cases, the DBS feature (only from this revision of SpeedStep) is also known to heavily utilize clock-gating to further reduce power consumption. |
Due to the massive changes done to SpeedStep's behavior, only some features remain controllable by user intervention (such as core voltage adjustment, and clock frequency adjustment). The features that are not controllable, are clock-gating, and the automatic shutdown of the CPU's internal components. | Due to the massive changes done to SpeedStep's behavior, only some features remain controllable by user intervention (such as core voltage adjustment, and clock frequency adjustment). The features that are not controllable, are clock-gating, and the automatic shutdown of the CPU's internal components. | ||
| − | The 'Banias' Pentium M | + | The 'Banias' Pentium M and the 'Prescott' Mobile Pentium 4, were the first to use this revision of SpeedStep. Newer Intel CPUs continue to utilize this revision of SpeedStep as well, although it was superseded by SpeedShift in newer Intel CPUs starting from Skylake. |
==Unreleased== | ==Unreleased== | ||
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Based off Geyserville-3, this was allegedly the enterprise variant of SpeedStep. It was originally supposed to be released in the form of 'Montecito' Itanium 2 CPUs, but it never materialized in the aforementioned CPUs. Only a concept exists for this particular revision of SpeedStep. | Based off Geyserville-3, this was allegedly the enterprise variant of SpeedStep. It was originally supposed to be released in the form of 'Montecito' Itanium 2 CPUs, but it never materialized in the aforementioned CPUs. Only a concept exists for this particular revision of SpeedStep. | ||
| − | Unlike Geyserville's aim to reduce power consumption for every possible situation, Foxton's aim is to maximize power consumption for every possible situation, while additionally staying in a designated thermal design point. For example (TDP is defined as 130 watts in this example), an application that uses very little computing power of a Foxton-enabled CPU may draw only 50 watts at maximum load. The Foxton-enabled CPU, in reaction to this, would step up the core voltage and clock frequency to maximize the given TDP of 130 watts. This operating principle is similar to Intel's newer Turbo Boost technology, but with the additional capability of varying that maximization by 64 frequency steps and 32 voltage steps (the concept defines each voltage step as 12.5 mV each, frequency is unknown). | + | Unlike Geyserville's aim to reduce power consumption for every possible situation, Foxton's aim is to maximize power consumption for every possible situation, while additionally staying in a designated thermal design point. For example (TDP is defined as 130 watts in this example), an application that uses very little computing power of a Foxton-enabled CPU may draw only 50 watts at maximum load. The Foxton-enabled CPU, in reaction to this, would step up the core voltage and clock frequency to maximize the given TDP of 130 watts. This operating principle is similar to Intel's newer [[Turbo Boost|Turbo Boost technology]], but with the additional capability of varying that maximization by 64 frequency steps and 32 voltage steps (the concept defines each voltage step as 12.5 mV each, frequency is unknown). |
| − | Due to Foxton's complexity, it has its own controller (dubbed as the 'Foxton Controller') to manage these features. The Foxton Controller is also known to run at half of the CPU's maximum clock frequency. | + | Due to Foxton's complexity, it has its own controller (dubbed as the 'Foxton Controller') to manage these features. The Foxton Controller is also known to run at half of the CPU's maximum clock frequency, for an unknown reason. Not much else is known about Foxton. |
[[Category:Glossary]] | [[Category:Glossary]] | ||
Latest revision as of 18:58, 15 November 2020
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On January 18th, 2000, Intel released its Mobile Pentium 3 600 MHz CPU with a proprietary power management technology called SpeedStep. This technology basically provides additional power saving modes for Intel's CPUs, it does not provide any sort of performance improvement. Please note that every revision of SpeedStep are similar and may be confusing, therefore this page will attempt to document the behavior of every known SpeedStep revision. |
Released
Intel SpeedStep Technology (Geyserville)
First introduced in the 'Coppermine' Mobile Pentium 3 CPUs ranging from 600-1000 MHz, it was extremely primitive in comparison to Transmeta's LongRun and AMD's PowerNow technologies. This is due to its bare-bones simplicity that consists of two power modes: 'Maximum Performance Mode' and 'Battery Optimized Mode'. Note that the two power modes had predefined core voltage and clock frequencies that could not be changed by software, as these were hard-wired during factory production.
Under AC power (in a charging or non-charging state), SpeedStep will automatically step into 'Maximum Performance Mode'. If the AC adapter is disconnected from the system, SpeedStep will automatically step into 'Battery Optimized Mode'. This behavior can be modified to some extent via issuing an instruction to either step into 'Maximum Performance Mode' without AC power, or step into 'Battery Optimized Mode' with AC power.
The 'Coppermine' Mobile Pentium 3 used this revision of SpeedStep. No other Intel CPU has used this revision of SpeedStep.
Enhanced Intel SpeedStep Technology (Geyserville-2)
This was a minor revision of the first SpeedStep that added a new feature called 'Demand-Based Switching'. The DBS function alters the CPU's current power mode state via monitoring the CPU's load, by making it operate in 'Maximum Performance Mode' under high to normal usage, and in 'Battery Optimized Mode' under low to no usage.
There were no major changes made to SpeedStep's behavior, other than the fact that the transition between the two basic power modes were now controlled by the DBS feature. However, SpeedStep could still be issued an instruction to always stay in 'Maximum Performance Mode' or 'Battery Optimized Mode'.
The 'Tualatin' Mobile Pentium 3-M, 'Northwood' Mobile Pentium 4-M, and the 'Northwood' Mobile Pentium 4, used this particular revision of SpeedStep for their power management capabilities.
Enhanced Intel SpeedStep Technology (Geyserville-3)
This was a major revision of SpeedStep, which removed the overly simple 'two power modes with hard-wired predefined values' concept. It now has the ability to operate on a wide range of frequencies by switching the CPU's clock multiplier (by 1x steps, not 0.5x steps), which was not the case for the two previous revisions of SpeedStep. Additionally, it has the capability of controlling the CPU's core voltage with more precision (by 16 mV steps, or lesser depending on the CPU model), unlike the previous revisions which used only two core voltages.
As SpeedStep was re-worked to take advantage of the aforementioned features, the behavior was also re-worked as well. In addition to the capability of controlling core voltage and clock frequencies via DBS, it is also capable of shutting down parts of the CPU to reduce power consumption, such as the L2 cache. In certain cases, the DBS feature (only from this revision of SpeedStep) is also known to heavily utilize clock-gating to further reduce power consumption.
Due to the massive changes done to SpeedStep's behavior, only some features remain controllable by user intervention (such as core voltage adjustment, and clock frequency adjustment). The features that are not controllable, are clock-gating, and the automatic shutdown of the CPU's internal components.
The 'Banias' Pentium M and the 'Prescott' Mobile Pentium 4, were the first to use this revision of SpeedStep. Newer Intel CPUs continue to utilize this revision of SpeedStep as well, although it was superseded by SpeedShift in newer Intel CPUs starting from Skylake.
Unreleased
Enhanced Intel SpeedStep Technology (Foxton)
Based off Geyserville-3, this was allegedly the enterprise variant of SpeedStep. It was originally supposed to be released in the form of 'Montecito' Itanium 2 CPUs, but it never materialized in the aforementioned CPUs. Only a concept exists for this particular revision of SpeedStep.
Unlike Geyserville's aim to reduce power consumption for every possible situation, Foxton's aim is to maximize power consumption for every possible situation, while additionally staying in a designated thermal design point. For example (TDP is defined as 130 watts in this example), an application that uses very little computing power of a Foxton-enabled CPU may draw only 50 watts at maximum load. The Foxton-enabled CPU, in reaction to this, would step up the core voltage and clock frequency to maximize the given TDP of 130 watts. This operating principle is similar to Intel's newer Turbo Boost technology, but with the additional capability of varying that maximization by 64 frequency steps and 32 voltage steps (the concept defines each voltage step as 12.5 mV each, frequency is unknown).
Due to Foxton's complexity, it has its own controller (dubbed as the 'Foxton Controller') to manage these features. The Foxton Controller is also known to run at half of the CPU's maximum clock frequency, for an unknown reason. Not much else is known about Foxton.
