Difference between revisions of "Intel Core Solo (Yonah)"
m |
(changed category) |
||
| (6 intermediate revisions by 6 users not shown) | |||
| Line 3: | Line 3: | ||
|style="vertical-align:top" | | |style="vertical-align:top" | | ||
<div style="margin: 0; margin-right:10px; border: 1px solid #dfdfdf; padding: 0em 1em 1em 1em; background-color:#F8F8FF; align:right;"> | <div style="margin: 0; margin-right:10px; border: 1px solid #dfdfdf; padding: 0em 1em 1em 1em; background-color:#F8F8FF; align:right;"> | ||
| − | |||
| − | |||
| − | + | The Intel Core Solo is the successor to the [[Intel_Pentium_M_(Dothan)|Pentium M processor]]. The chip uses Intel's 65 nm process (compared to 90 nm for the Pentium M). The Intel Core processors feature a 667 MHz FSB and are shipped as part of the Napa Centrino platform. | |
| − | *1.66 GHz clock speed | + | |
| − | *667 MHz FSB | + | ==Features== |
| − | *27 watt thermal design power consumption | + | *1.2 - 1.66 GHz clock speed |
| + | *667 MHz FSB; 533 MHz for ULV CPU | ||
| + | *5.5 (ultra low voltage) or 27 (normal voltage) watt thermal design power consumption | ||
*151 Million Transistors | *151 Million Transistors | ||
*65 nm process | *65 nm process | ||
*2 MB L2-Cache | *2 MB L2-Cache | ||
| − | *[[SpeedStep|Enhanced Intel SpeedStep (EIST)]], power states: normal (C0), AutoHALT/MWAIT (C1), Stop Grant (C2), Deep Sleep (C3), Deeper Sleep (C4) | + | *[[SpeedStep|Enhanced Intel SpeedStep (EIST)]], power states: normal (C0), AutoHALT/MWAIT (C1), Stop Grant (C2), Deep Sleep (C3), [[QuickStart and Deeper Sleep|Deeper Sleep]] (C4) |
*[[SIMD|MMX]], [[SIMD|SSE]], [[SIMD|SSE2]], [[SIMD|SSE3]] instruction sets, XD-Bit | *[[SIMD|MMX]], [[SIMD|SSE]], [[SIMD|SSE2]], [[SIMD|SSE3]] instruction sets, XD-Bit | ||
</div> | </div> | ||
| Line 27: | Line 27: | ||
! colspan="10" | Intel Core Solo | ! colspan="10" | Intel Core Solo | ||
|- | |- | ||
| − | | T1300 || 1666 || 1000 || 667 || yes || 1.2 || ... || 27 || 13.1 || {{X60}}, {{T60}} | + | | T1300 || 1666 || 1000 || 667 || yes || 1.2 || ... || 27 || 13.1 || {{X60}}, {{T60}} |
| + | |- | ||
| + | | U1400 || 1200 || 800 || 533 || yes || 1.1 || ... || 5.5 || 5 || {{X60t}} | ||
|} | |} | ||
| Line 34: | Line 36: | ||
==GCC Optimization Flags== | ==GCC Optimization Flags== | ||
| + | Safe, recommended optimizations for GCC 3.4.x and later: | ||
| + | -pipe -O2 -march=prescott -fomit-frame-pointer | ||
| + | |||
| + | Possibly unsafe optimizations for GCC 3.3.x and later: | ||
| + | -mfpmath=sse | ||
| + | |||
| + | Optimizations likely to break binary-only compatibility: | ||
| + | -ffast-math | ||
==See also== | ==See also== | ||
[[Intel_Core_Duo_(Yonah)|Intel Core Duo (Yonah)]] | [[Intel_Core_Duo_(Yonah)|Intel Core Duo (Yonah)]] | ||
| − | [[Category: | + | [[Category:CPUs]] |
Latest revision as of 15:50, 22 January 2021
|
The Intel Core Solo is the successor to the Pentium M processor. The chip uses Intel's 65 nm process (compared to 90 nm for the Pentium M). The Intel Core processors feature a 667 MHz FSB and are shipped as part of the Napa Centrino platform. Features
|
Available Types and ThinkPads featuring them
| Nr. | Frequency (MHz) | FSB (MHz) | XD-Bit | core Voltage (V) | TDP (W) | ThinkPad Models | |||
|---|---|---|---|---|---|---|---|---|---|
| max. | min. | high | low | high | low | ||||
| Intel Core Solo | |||||||||
| T1300 | 1666 | 1000 | 667 | yes | 1.2 | ... | 27 | 13.1 | X60, T60 |
| U1400 | 1200 | 800 | 533 | yes | 1.1 | ... | 5.5 | 5 | X60 Tablet |
Thermal Specifications
The maximum temperature for safe operation is 100 °C.
GCC Optimization Flags
Safe, recommended optimizations for GCC 3.4.x and later:
-pipe -O2 -march=prescott -fomit-frame-pointer
Possibly unsafe optimizations for GCC 3.3.x and later:
-mfpmath=sse
Optimizations likely to break binary-only compatibility:
-ffast-math
